1. Field of the Invention
The present invention relates to a through-hole layout apparatus and a through-hole layout method.
2. Description of Related Art
In semiconductor integrated-circuits in general, through-holes are provided for interconnecting wirings in upper and lower layer wirings.
In designing a semiconductor integrated-circuit, through-holes are densely placed in some regions and sparsely placed in other regions on each wiring layer because the through-holes occupy a small area of the data area of each wring layer. Here, the data area is the area to which a process is actually applied by exposure and masking.
FIG. 1A shows an example of a layout based on semiconductor integrated circuit design data according to the related art. FIG. 1B shows a pattern of through-holes extracted from the layout shown in FIG. 1A. It can be seen from the extracted through-hole pattern in FIG. 1B that there are regions where through-holes 303 are densely placed and regions where through-holes 303 are sparsely placed.
It is known that through-holes in a sparsely placed region tend to be deformed by defocusing during a diffusion step for processing through-holes in a semiconductor integrated circuit fabrication process as compared with those in a densely placed region. Deformation of through-holes 303 causes problems such as an increase in the resistance of a contact between upper layer wiring 301 and lower layer wiring 302 or an imperfectly opening a through-hole to interconnect upper layer 301 and lower layer wiring 302.
Thus, differences in the layout density of though-holes cause variations in shapes and dimensions of formed through-holes, leading to yield loss of the semiconductor integrated circuit.
To solve the yield loss problem due to differences in layout density of through-holes, techniques are disclosed in Japanese Patent Laid-Open No. 2005-251796 (hereinafter referred to as Patent Document 1) and No. 2006-049534 (hereinafter referred to as Patent Document 2) that make the shapes of through-holes uniform.
In the technique described in Patent Document 1, a dummy pattern is added that includes slits surrounding each through-hole and the width of the dummy pattern and the distance between the slit and each through-hole are controlled to adjust the amount of shrinkage during processing of the through-holes, thereby making the shapes of the through-holes uniform.
In the technique described in Patent Document 2, instead of through-holes, dummy patterns that are smaller than through-holes are provided around the through-holes in a region where through-holes are sparsely placed to avoid variations in density in the process pattern during through-hole processing, thereby making the shapes of the through-holes uniform. The dimensions of the dummy pattern are adjusted so that the dummy patterns do not pass through the upper and lower layer wirings during processing of the through-holes.
However, the techniques described in Patent Documents 1 and 2 have the following problems.
In the techniques disclosed in Patent Documents 1 and 2, the dummy pattern, which is not specified in a process design criterion which is a set of design rules for a semiconductor integrated circuit, is added to design data. Accordingly, exposure conditions need to be determined by using an additional optical simulation by taking the dummy pattern into consideration to determine the amount of optical correction and a data process flow. Consequently, the number of development steps significantly increases.
Another problem with the techniques described in Patent Documents 1 and 2 is that addition of a dummy pattern to semiconductor integrated circuit design data adds to the complexity of the process of inspection of the semiconductor integrated circuit.